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| as1324 1.5mhz, 600ma, dc/dc step-down regulator data sheet www.austriamicrosystems.com revision 1.03 1 - 20 1 general description the as1324 is a high-efficiency, constant-frequency synchronous buck converter available in adjustable- and fixed-voltage versions. the wide input voltage range (2.7v to 5.5v), automatic powersave mode and minimal external component requirements make the as1324 perfect for any single li-ion battery-powered application. typical supply current with no load is 30a and decreases to 1a in shutdown mode. the as1324 is available as the standard versions listed in table 1 . an internal synchronous swit ch increases efficiency and eliminates the need for an external schottky diode. the internally fixed switching frequency (1.5mhz) allows for the use of small surface mount external components. very low output voltages can be delivered with the inter- nal 0.6v feedback reference voltage. the as1324 is available in a 5-pin tsot-23 package. 2 key features high efficiency: up to 96% output current: 600ma input voltage range: 2.7v to 5.5v constant frequency operation: 1.5mhz variable- and fixed-output voltages no schottky diode required automatic powersave operation low quiescent current: 30a internal reference: 0.6v shutdown mode supply current: 1a thermal protection 5-pin tsot-23 package 3 applications the device is ideal for mobile communication devices, laptops and pdas, ultra-lo w-power systems, threshold detectors/discriminators, te lemetry and re mote systems, medical instruments, or any other space-limited applica- tion with low power-consumption requirements. table 1. standard versions model output voltage as1324-ad adjustable via external resistors as1324-12 fixed: 1.2v as1324-15 fixed: 1.5v as1324-18 fixed: 1.8v figure 1. typical application diagram ? high efficiency step down converter as1324- 18 c out 10f c in 10f gnd 2 v in = 2.7v to 5.5v v out = 1.8v, 600ma 4.7h 1 en 5 vout 4 vin 3 sw 5 vout as1324- 18 4 vin 2 gnd 3 sw 1 en
www.austriamicrosystems.com revision 1.03 2 - 20 as1324 data sheet - pinout and packaging 4 pinout and packaging pin assignments figure 2. pin assignments (top view) pin descriptions table 2. pin descriptions pin number pin name description 1en enable input . driving this pin above 1.5v enables t he device. driving this pin below 0.3v puts the device in shutdown mode. in shutdown mode all functions are disabled while sw goes high impedance, drawing <1a supply current. note: this pin should not be left floating. 2gnd ground. 3sw switch node connection to inductor. this pin connects to the drains of the internal main and synchronous power mosfet switches. 4vin input supply voltage . this pin must be closely decoupled to gnd with a 4.7f ceramic capacitor. connect to any supply voltage between 2.7 to 5.5v. 5 vfb feedback pin . this pin receives the feedback voltage from the external resistor divider across the output. (adjustable voltage variant only.) vout output voltage feedback pin . an internal resistor divider steps the output voltage down for comparison to the internal reference voltage. (fixed voltage variants only.) 5 vfb as1324 4vin 2 gnd 3 sw 1 en 5 vout as1324-12/ as1324-15/ as1324-18 4vin 2 gnd 3 sw 1 en www.austriamicrosystems.com revision 1.03 3 - 20 as1324 data sheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 3 may cause permanent damage to the device. these are stress ratings only, and functional operation of the de vice at these or any other cond itions beyond those indicated in section 6 electrical characteristics on page 4 is not implied. exposure to absolute maxi mum rating conditions for extended periods may affect device reliability. table 3. absolute maximum ratings parameter min max units comments vin to gnd -0.3 7 v sw, en, fb to gnd -0.3 v in + 0.3 v thermal resistance ja 207.4 oc/w on pcb esd 2 kv hbm mil-std. 883e 3015.7 methods latch-up -100 +100 ma jedec 78 operating temperature range -40 +85 oc storage temperature range -65 +125 oc package body temperature +260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/jedec j-std-020c ?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices?. the lead finish for pb-free leaded packages is matte tin (100% sn). junction temperature 125 oc junction temperature (t j ) is calculated from the ambient temperature (t amb ) and power dissipation (pd) as: t j = t amb + (pd)(207.4oc/w) (eq 1) www.austriamicrosystems.com revision 1.03 4 - 20 as1324 data sheet - electrical characteristics 6 electrical characteristics v in = en = 3.6v, v out < v in - 0.5v, t amb = -40 to +85c, typ. values @ t amb = +25oc (unless otherwise specified). table 4. electrical characteristics symbol parameter conditions min typ max units v in input voltage range 2.7 5.5 v i q quiescent current powersave mode; v fb = 0.62v or v out = 103%, i out = 0ma, t amb = +25oc 30 35 a i shdn shutdown current shutdown mode; v en = 0v, t amb = +25oc 0.1 1 regulation v fb regulated feedback voltage 1 1. the device is tested in a proprietary test mode where v fb is connected to the output of the error amplifier. as1324, i out = 100ma 0.585 0.6 0.615 v v fb reference voltage line regulation v in = 2.7v to 5.5v 0.1 1 %/v i vfb feedback current t amb = +25oc -30 30 na v out regulated output voltage as1324-ad, i out = 100ma 2 2. please see feedback resistor selection on page 13 for resistor values. v fb v as1324-12, i out = 100ma 1.164 1.20 1.236 as1324-15, i out = 100ma 1.455 1.50 1.545 as1324-18, i out = 100ma 1.746 1.80 1.854 v out output voltage line regulation v in = 2.7 to 5.5v 0.1 1 %/v v loadreg output voltage load regulation i out = 0 to 100ma 0.02 %/ma dc-dc switches i pk peak inductor current v in = 3v, v fb = 0.5v or v out = 90%, t amb = 25oc 0.5 0.75 1 a r pfet p-channel fet r ds(on) i lsw = 100ma 0.4 r nfet n-channel fet r ds(on) i lsw = -100ma 0.35 i lsw sw leakage v en = 0v, v sw = 0v or 5v 0.01 1 a control inputs v en en threshold 0.3 1 1.5 v i en en leakage current 0.01 1 a oscillator f osc oscillator frequency v fb = 0.6v or v out = 100% 1.2 1.5 1.8 mhz v fb = 0v or v out = 0v, t amb = 25oc 115 khz www.austriamicrosystems.com revision 1.03 5 - 20 as1324 data sheet - typical operating characteristics 7 typical operating characteristics parts used for measurement: 4.7h (mos6020- 472) inductor, 10f (grm188r60j106me47) c in and c out . figure 3. efficiency vs. input voltage; v out = 1.8v figure 4. efficien cy vs. output current; v out = 1.2v 50 55 60 65 70 75 80 85 90 95 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 input voltage (v) efficiency (%) . iout = 600ma iout = 100 ma iout = 10ma iout = 1ma 50 55 60 65 70 75 80 85 90 95 100 1 10 100 1000 output current (ma) efficiency (%) . vin = 2.5v vin = 2.7v vin = 3.7v vin = 4.2v v in = 5.5v figure 5. efficiency vs. output current; v out = 1.5v figure 6. efficiency vs. output current; v out = 1.8v 50 55 60 65 70 75 80 85 90 95 100 1 10 100 1000 output current (ma) efficiency (%) . vin = 2.5v vin = 2.7v vin = 3.7v vin = 4.2v v in = 5.5v 50 55 60 65 70 75 80 85 90 95 100 1 10 100 1000 output current (ma) efficiency (%) . vin = 2.5v vin = 2.7v vin = 3.7v vin = 4.2v v in = 5.5v figure 7. efficiency vs. output current; v out = 2.5v figure 8. effici ency vs. output current; v out = 3.3v 50 55 60 65 70 75 80 85 90 95 100 1 10 100 1000 output current (ma) efficiency (%) . vin = 3.7v vin = 4.2v v in = 5.5v 50 55 60 65 70 75 80 85 90 95 100 1 10 100 1000 output current (ma) efficiency (%) . vin = 4.2v v in = 5.5v www.austriamicrosystems.com revision 1.03 6 - 20 as1324 data sheet - typical operating characteristics figure 9. switching frequency vs. supply voltag e figure 10. switching frequency vs. temperature 1.4 1.45 1.5 1.55 1.6 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 input voltage (v) switching frequency (mhz) . 1.4 1.45 1.5 1.55 1.6 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) switching frequency (mhz) . figure 11. feedback voltage vs. temperature figure 12. output voltage vs. input voltage 0.59 0.595 0.6 0.605 0.61 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) feedback voltage (v) . 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95 2 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 input voltage (v) output voltage (v) . iout = 600ma iout = 100 ma iout = 10ma iout = 1ma iout = 100 a figure 13. v out vs. i out ; v outnom = 1.2v figure 14. v out vs. i out ; v outnom = 1.5v 1.1 1.15 1.2 1.25 1.3 0 100 200 300 400 500 600 output current (ma) output voltage (v) . v in=2 .5v v in=2 .7v v in=5.5v 1.4 1.45 1.5 1.55 1.6 0 100 200 300 400 500 600 output current (ma) output voltage (v) . v in=2 .5v v in=2 .7v v in=5.5v www.austriamicrosystems.com revision 1.03 7 - 20 as1324 data sheet - typical operating characteristics figure 15. quiescent current vs. input voltage f igure 16. quiescent current vs. temperature 0 5 10 15 20 25 30 35 40 45 50 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 input voltage (v) quiescent current (a) . 0 5 10 15 20 25 30 35 40 45 50 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) quiescent current (a) . figure 17. load step 0ma to 600ma figure 18. load step 10ma to 200ma i sw v out i out 500ma/div 200mv/div 500s/div 600ma/div 500ma/div 200mv/div i sw 500s/div v out i out 200ma/div figure 19. startup figure 20. powersave mode 560ma/div 5v/div en i sw 1ms/div v out 1v/div 100mv/div 5v/div v sw i sw 5s/div v out 200ma/div www.austriamicrosystems.com revision 1.03 8 - 20 as1324 data sheet - detailed description 8 detailed description the as1324 is a high-efficiency buck converter that uses a constant-frequency current-mode architecture. the device contains two internal mosfet switches and is availa ble in adjustable- and fixed-output voltage versions. figure 21. block diagram main control loop during pwm operation the converters use a 1.5mhz fixed-fr equency, current-mode control scheme. basis of the cur- rent-mode pwm controller is an open-loop, multiple input comparator that compares the error-amp voltage feedback signal against the sum of the amplified current-sense signal and the slope-compensation ramp. at the beginning of each clock cycle, the internal high-side pmos turns on until the pwm comparator trips. during this time the current in the inductor ramps up, sourcing current to the output an d storing energy in the inductor?s magnetic field. when the pmos turns off, the internal low-side nmos turns on. no w the inductor releases the stored energy while the current ramps down, still providing current to the output. the outp ut capacitor stores charge when the inductor current exceeds the load and discharges when the inductor current is lower than the load. under overload conditions, when the inductor current exceeds the current limit, the high -side pmos is turned off and the low-side nmos remains on until the next clock cycle. when the pmos is off, the nmos is turned on until the inductor current starts to reverse (as indicated by the current reversal comparator (ircmp)), or the next clock cycle begins. the ir cmp detects the zero crossing. the peak inductor current (i pk ) is controlled by the error amplifier. when i out increases, v fb decreases slightly relative to the internal 0.6v reference, causing the error amplifier?s output voltage to increase until the average inductor current matches the new load current. the over-voltage detection comparator (ovdet) guards agains t transient overshoots by turning the main switch off and keeping it off until the transient is removed. as1324 osc frequency shift 0.6v reference + ? error amp shutdown ramp compensator r 2 0.6v fb oscn digital logic 0.6v + v ovl 0.6v - v ovl ? ovdet + ? + ? icomp + ? ircmp + anti- shoot through not applicable to as1324 as1324-12: r 1 + r 2 = 600k as1324-15: r 1 + r 2 = 750k as1324-18: r 1 + r 2 = 900k r 1 pmos 1 en 5 v out /v fb 4 v in 3 sw 2 gnd nmos c out 10f v out 4.7h c in 10f v in www.austriamicrosystems.com revision 1.03 9 - 20 as1324 data sheet - detailed description powersave operation the as1324 uses an automatic powersave mode where the peak inductor current (i pk ) is set to approximately 200ma while independent of the output load. in powersave mode, load current is supplied solely from the output capacitor. as the output voltage drops, the error amplifier output rises above the powersave threshold signaling to switch into pwm fixed frequency mode and turn the pmos on. this process repeats at a rate determined by the load demand. each burst event can last from a few cycles at light loads to almost continuous cycling (with short sleep intervals) at moderate loads. in between bursts, the power mosfets are turned off, as is any unneeded circuitry, reducing quies- cent current to 30a. short-circuit protection in cases where the as1324 output is shorted to ground, the oscillator frequency (f osc ) is reduced to 1/13 the nominal frequency ( ? 115khz). this frequency reduction ensures that the inductor current has more time to decay, thus pre- venting runaway conditions. f osc will progressively increase to 1.5mhz when v fb /v out > 0v. shutdown connecting en to gnd or logic low places the as1324 in sh utdown mode and reduces the supply current to 0.1a. in shutdown the control circuitry and the internal nmos and pmos turn off and sw becomes high impedance discon- necting the input from the output. the output capacitance and load current determine the voltage decay rate. for nor- mal operation connect en to v in or logic high. note: pin en should not be left floating. www.austriamicrosystems.co m revision 1.03 10 - 20 as1324 data sheet - application information 9 application information the as1324 is perfect for mobile communications equipment like cell phones and smart phones, digital cameras and camcorders, portabel mp3 and dvd players, pda?s and pa lmtop computers and any other handheld instruments. figure 22. single li-ion 1.2v/600 ma regulator for high-efficiency figure 23. 5v input to 3.3v/600ma buck regulator figure 24. single li-ion 1.5v/600 ma regulator for high-efficiency as1324 c out 10f c in 2.2f v in 2.7 to 4.2v v out 1.2v 600ma 4.7h 301k 22pf 301k r 2 r 1 3 sw 4 v in 1 en 5 v fb gnd 2 c out 10f c in 4.7f v in 5v v out 3.3v 600ma 4.7h 66.5k 22pf 301k r 2 r 1 as1324 3 sw 4 v in 1 en 5 v fb gnd 2 c out 10f c in 4.7f v in 2.7 to 4.2v v out 1.5v 600ma 4.7h as1324- 15 3 sw 4 v in 1 en 5 v out gnd 2 www.austriamicrosystems.co m revision 1.03 11 - 20 as1324 data sheet - application information figure 25. single li-ion 1.8v/600ma regulator for low output ripple external component selection inductor selection for most applications the value of the external inductor should be in the range of 2.2 to 6.8h as the inductor value has a direct effect on the ripple current. the selected inductor must be rated for its dc resistance and saturation cur- rent. the inductor ripple current ( i l ) decreases with higher inductance and increases with higher v in or v out . in equation (eq 2) the maximum inductor current in pwm mode under static load conditions is calculated. the satura- tion current of the inductor should be rated higher than the maximum inductor current as calculated with equation (eq 3) . this is recommended because the inductor current will rise above the calculated value during heavy load tran- sients. where: f = switching frequency (1.5 mhz typical) l = inductor value i lmax = maximum inductor current i l = peak to peak inductor ripple current the recommended starting point for setting ripple current is i l = 240ma (40% of 600ma). the dc current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. thus, a 720ma rated inductor should be sufficient for most applications (600ma + 120ma). a easy and fast approach is to select the inductor current rating fitting to the maximum switch current limit of the con- verter. note: for highest efficiency, a low dc-resistance inductor is recommended. accepting larger values of ripple current allows the use of low inductance values, but results in higher output voltage ripple, greater core losses, and lower output current capability. c out 22f c in 10f v out 1.8v 600ma 4.7h v in 2.7 to 4.2v as1324- 18 3 sw 4 v in 1 en 5 v out gnd 2 (eq 2) i l v out 1 v out v in -------------- ? lf ----------------------- - = (eq 3) i lmax i outmax i l 2 -------- + = www.austriamicrosystems.co m revision 1.03 12 - 20 as1324 data sheet - application information the total losses of the coil have a strong impact on the efficiency of the dc/dc conversion and consist of both the losses in the dc resistance and the following frequency-dependent components: 1. the losses in the core material (magnetic h ysteresis loss, especially at high switching frequencies) 2. additional losses in the conductor from the skin effect (current displacement at high frequencies) 3. magnetic field losses of the neighboring windings (proximity effect) 4. radiation losses figure 26. efficiency comparison of different inductors, v in = 2.7v, v out = 1.8v and 1.2v output capacitor selection the advanced fast-response voltage mode control scheme of th e as1324 allows the use of tiny ceramic capacitors. because of their lowest output voltage ripple low esr ceramic capacitors are recommended. x7r or x5r dielectric output capacitor are recommended. at high load currents, the device operates in pwm m ode and the rms ripple current is calculated as: while operating in pwm mode the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor esr plus the voltage ripple caused by charging and discharging the output capacitor: table 5. recommended inductors part number l dcr current rating dimensions (l/w/t) manufacturer lqh32cn2r2m33 2.2h 97m 790ma 3.2x2.5x2.0mm murata www.murata.com lqh32cn4r7m33 4.7h 150m 650ma 3.2x2.5x2.0mm lps3008-222mlc 2.2h 175m 1100ma 3.1x3.1x0.8mm coilcraft www.coilcraft.com lps3015-222mlc 2.2h 110m 2000ma 3.1x3.1x1.5mm mos6020-222mlc 2.2h 35m 3260ma 6.0x6.8x2.4mm mos6020-472mlc 4.7h 50m 1820ma 6.0x6.8x2.4mm cdrh3d16np-2r2n 2.2h 72m 1200ma 4.0x4.0x1.8mm sumida www.sumida.com cdrh3d16nd-4r7n 4.7h 105m 900ma 4.0x4.0x1.8mm 70 75 80 85 90 95 1 10 100 1000 output current (ma) efficiency (%) . lqh32cn2r2 lps3008-222 lps3 0 15- 2 2 2 mos6020-222 lqh32cn4r7 mos6020-472 70 75 80 85 90 95 1 10 100 1000 output current (ma) efficiency (%) . lqh32cn2r2 lps3008-222 lps3 0 15-2 2 2 m os6020-22 2 lqh32cn4r7 m os6020-472 v out = 1.8v v out = 1.2v (eq 4) i rmsc out v out 1 v out v in -------------- ? lf ----------------------- - 1 23 ---------------- - = (eq 5) v out v out 1 v out v in -------------- ? lf ----------------------- - 1 8c out f -------------------------------- esr + ?? ?? = www.austriamicrosystems.co m revision 1.03 13 - 20 as1324 data sheet - application information higher value, low cost ceramic capacitors are available in very small case sizes, and their high ripple current, high volt- age rating, and low esr make them ideal for switching regulator applications. because the as1324 control loop is not dependant on the output capacitor esr for stable operation, ceramic capacitors can be used to achieve very low out- put ripple and accommodate small circuit size. at light loads, the converter operates in powersave mode and the output voltage ripple is in direct relation to the output capacitor and inductor value used. larger output capacitor and inductor values minimize the voltage ripple in power- save mode and tighten dc output accuracy in powersave mode. input capacitor selection in continuous mode, the source current of thepmos is a s quare wave of the duty cycle v out /v in . to prevent large volt- age transients while minimizing the interference with other circuits caused by high input voltage spikes, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given as: where the maximum average output current i max equals the peak current minus half the peak-to-peak ripple current, i max = i lim - i l /2 this formula has a maximum at v in = 2v out where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations only provide negligible affects. the input capacitor can be increased without any limit for better input voltage filtering. take care when using small ceramic input capacitors. when a small ceramic capacitor is used at the input, and the power is being supplied through long wires, such as from a wall adapter, a load step at the output, or v in step on the input, can induce ringing at the vin pin. this ringing can then couple to the output and be mistaken as loop instability, or could even damage the part by exceeding the maximum ratings. ceramic input and output capacitors when choosing ceramic capacitors for c in and c out , the x5r or x7r dielectric formulations are recommended. these dielectrics have the best temperature and voltage characteristics for a given value and size. y5v and z5u dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequen- cies and therefore should not be used. because ceramic capacitors lose a lot of their initial capacitance at their maximum rated voltage, it is recommended that either a higher input capacity or a ca pacitance with a higher rated voltage is used. feedback resistor selection in the as1324-ad, the output voltage is set by an external resistor divider connected to v fb (see figure 27) . this cir- cuitry allows for remote voltage sensing and adjustment. table 6. recommended input and output capacitor part number c tc code rated voltage dimensions (l/w/t) manufacturer jmk212bj226mg-t 22f x5r 6.3v 0805 ta i y o yu d e n www.t-yuden.com grm188r60j106me47 10f x5r 6.3v 0603 murata www.murata.com grm21br71a475ka73 4.7f x7r 10v 0805 (eq 6) i rms i max v out v in v out ? () v in ----------------------------------------------------------- - = www.austriamicrosystems.co m revision 1.03 14 - 20 as1324 data sheet - application information figure 27. setting the as1324 output voltage resistor values for the circuit shown in figure 27 can be calculated as: the output voltage can be adjusted by selecting different values for r 1 and r 2 . for r 1 a value between 10k and 500k is recommended. a higher resistance of r 1 and r 2 will result in a lower leakage current at the output. it is rec- ommended to keep v in 500mv higher than v out . efficiency the efficiency of a switching regulator is equivalent to: efficiency = (p out /p in )100% (eq 8) for optimum design, an analysis of the as1324 is needed to determine efficiency limitations and to determine design changes for improved efficiency. efficiency can be expressed as: efficiency = 100% ? (l 1 + l 2 + l 3 + ...) (eq 9) where: l 1 , l 2 , l 3 , etc. are the individual losses as a percentage of input power. althought all dissipative elements in the circuit produce lo sses, those four main sources should be considered for effi- ciency calculation: input voltage quiescent current losses the v in current is the dc supply current given in the electrical characteristics which excludes mosfet driver and con- trol currents. v in current results in a small (<0.1%) loss that increases with v in , even at no load. the v in quiescent cur- rent loss dominates the efficiency loss at very low load currents. i2r losses most of the efficiency loss at medium to high load currents are attributed to i2r loss, and are calculated from the resis- tances of the internal switches (r sw) and the external inductor (r l ). in continuous mode, the average output current flowing through inductor l is split between the internal swit ches. therefore, the series resistance looking into the sw pin is a function of both nmos & pmos r ds(on) as well as the the duty cycle (dc) and can be calculated as follows: r sw = (r ds(on)pmos )(dc) + (r ds(on)nmos )(1 ? dc) (eq 10) the r ds(on) for both mosfets can be obtained from the electrical characteristics on page 4 . thus, to obtain i2r losses calculate as follows: i2r losses = i out 2(r sw + r l )(eq 11) switching losses the switching current is the sum of the control currents and the mosfet driver. the mosfet driver current results from switching the gate capacitance of the power mosfets. if a mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of v in that is typically much larger than the dc bias current. in continuous mode: i gc = f(q pmos + q nmos )(eq 12) where: q pmos and q nmos are the gate charges of the internal mosfet switches. the losses of the gate charges are proportional to v in and thus their effects will be more visible at higher supply volt- ages. other losses r 2 0.6v v out 5.5v r 1 as1324 5 v fb 2 gnd r 1 < www.austriamicrosystems.co m revision 1.03 16 - 20 as1324 data sheet - application information for best overall efficiency use an inductor with a rating of 720ma or greater and less than 0.2 series resistance. c in will require an rms current rating of at least 0.3a ? i load(max) /2, whereas c out will require an esr of less than 0.25 . in most cases, a ceramic capacitor will satisfy this requirement. for the feedback resistors, select the value for r 1 = 375k . r 2 can then be calculated from (eq 7) to be: r 2 = (v out /0.6 - 1)375k = 1000k layout considerations the as1324 requires proper layout and design techniques for optimum performance. the power traces (gnd, sw, and v in ) should be kept as short, direct, and wide as is practical. pin v fb (as1324 only) should be connected directly to the feedback resistors (r 1 and r 2 ). a potentiometer as replacement for r 1 and r 2 should be avoided to minimize the output voltage ripple and to maintain the stability of the regulator. the resistive divider (r 1 /r 2 ) must be connected between the positive plate of c out and ground. the positive plate of c in should be connected as close to v in as is practical since c in provides the ac current to the internal power mosfets. switching node sw should be kept far away from the sensitive v fb node. the negative plates of c in and c out should be kept as close to each other as is practical. a starpoint to ground is recommended. figure 29. as1324 basic pcb layout figure 30. as1324 basic diagram 5 as1324 4 3 2 1 via to gnd via to v out v out sw gnd v in via to v in c out c in l 1 r 1 r 2 c fwd as1324 1 en 4 vin 3 sw 5 vfb 2 gnd c in l 1 r 1 r 2 c fwd high current path v in c out v out www.austriamicrosystems.co m revision 1.03 17 - 20 as1324 data sheet - application information figure 31. as1324-18 basic pcb layout figure 32. as1324-18 basic diagram 5 as1324- 18 4 3 2 1 v out sw gnd v in c out c in l 1 via to v in via to v out as1324-18 1 en 4 vin 3 sw 5 vout 2 gnd v in c in l 1 high current path c out v out www.austriamicrosystems.co m revision 1.03 18 - 20 as1324 data sheet - pack age drawings and markings 10 package drawings and markings the device is available in an 5-pin tsot-23 package. figure 33. 5-pin tsot-23 package notes: 1. dimensioning and tolerancing conform to asme y14.5m - 1994. 2. dimensions are in millimeters. 3. dimension d does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, and gate burrs shall not exceed 0.15mm per end. dimension e1 does not include interlead flash or protrusion. interlead flash or pro- trusion shall not exceed 0.15mm per side. dime nsions d and e1 are determined at datum h. 4. the package top can be smaller than the package bottom. dimensions d and e1 are determined at the outer- most extremes of the plastic body exclusive of mold fl ash, tie bar burrs, gate burrs, and interlead flash, but include any mistmatches between the top of the package body and the bottom. d and e1 are determined at datum h. symbol min typ max notes symbol min typ max notes a 1.00 l 0.30 0.40 0.50 a1 0.01 0.05 0.10 l1 0.60ref a2 0.84 0.87 0.90 l2 0.25bsc b 0.30 0.45 n 5 b1 0.31 0.35 0.39 r 0.10 c 0.12 0.15 0.20 r1 0.10 0.25 c1 0.08 0.13 0.16 0o 4o 8o d 2.90bsc 3,4 1 4o 10o 12o e 2.80bsc 3,4 tolerances of form and position e1 1.60bsc 3,4 aaa 0.15 e 0.95bsc bbb 0.25 e1 1.90bsc ccc 0.10 ddd 0.20 www.austriamicrosystems.co m revision 1.03 19 - 20 as1324 data sheet - ordering information 11 ordering information the device is available as the following standard versions. all devices are rohs compliant and free of halogene substances. table 7. ordering information model marking output description delivery form package as1324-bttt-ad askr adjustable 1.5mhz, 600ma synchronous dc/dc converter tape and reel 5-pin tsot-23 AS1324-BTTT-12 askt 1.2v 1.5mhz, 600ma synchronous dc/dc converter tape and reel 5-pin tsot-23 as1324-bttt-15 asku 1.5v 1.5mhz, 600ma synchronous dc/dc converter tape and reel 5-pin tsot-23 as1324-bttt-18 asks 1.8v 1.5mhz, 600ma synchronous dc/dc converter tape and reel 5-pin tsot-23 www.austriamicrosystems.co m revision 1.03 20 - 20 as1324 data sheet copyrights copyright ? 1997-200 9, austriamicrosystems ag, schloss premstaett en, 8141 unterpremstae tten, austria-europe. trademarks registered ?. all rights reserved. the materi al herein may not be reproduced, adapted, merged, trans- lated, stored, or used without the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by t he warranty and patent indemni fication provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austria- microsystems ag reserves the right to change specifications and pr ices at any time and wi thout notice. therefore, prior to designing this product into a syst em, it is necessary to check with aust riamicrosystems ag for current informa- tion. this product is intended for use in normal commercia l applications. applications requiring extended temperature range, unusual environmental requirements, or high reliability app lications, such as military, medical life-support or life- sustaining equipment are specifically not recommended withou t additional processing by austriamicrosystems ag for each application. for shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or ar ising out of the furnishing, performance or use of the tech- nical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag a-8141 schloss premstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.austriamicr osystems.com/contact-us |
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